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(R)
STD15NF10
N - CHANNEL 100V - 0.073 - 15A TO-252 LOW GATE CHARGE STripFETTM POWER MOSFET
PRELIMINARY DATA TYPE STD15NF10
s s s s
V DSS 100 V
R DS( on ) < 0.08
ID 15 A
s
TYPICAL RDS(on) = 0.073 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX "T4")
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DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements. APPLICATIONS s HIGH-EFFICIENCY DC-DC CONVERTERS s UPS AND MOTOR CONTROL
DPAK TO-252
(Suffix "T4")
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symb ol V DS V DGR VGS ID ID I DM (*) P tot dv/dt(1 ) E AS (2) T st g Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage Drain Current (continuous) at Tc = 25 oC Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature
o
Value 100 100 20 15 10 60 45 0.3 9 75 -65 to 175 175
Unit V V V A A A W W /o C V/ns mJ
o o
C C 1/6
Max. Operating Junction Temperature Tj (*) Pulse width limited by safe operating area ( 2) starting Tj = 25 oC, ID =24A , VDD = 50V April 2000
(1) I SD 80 A, di/dt 300A/s, VDD V(BR)DSS, Tj TJMA
STD15NF10
THERMAL DATA
R thj -case R thj -amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature F or Soldering Purpose 3.33 62.5 300
o o
C/W C/W o C
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 A V GS = 0 Min. 100 1 10 100 Typ. Max. Unit V A A nA
V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = 20 V
T c =125 oC
ON ()
Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10 V Test Con ditions ID = 250 A ID = 7.5 A 15 Min. 2 Typ. 3 0.073 Max. 4 0.08 Unit V A
V DS > ID(o n) x R DS(on )ma x V GS = 10 V
DYNAMIC
Symbo l g f s () C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz I D =7.5 A V GS = 0 Min. Typ. 20 870 125 52 Max. Unit S pF pF pF
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STD15NF10
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay T ime Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 50 V I D = 12 A R G = 4.7 V GS = 10 V (Resistive Load, see fig. 3) V DD = 80 V ID = 15 A V GS = 10 V Min. Typ. 58 45 30 6 10 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbo l t d(of f) tf t d(of f) tf tc Parameter Turn-off Delay T ime Fall T ime Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions V DD = 27 V I D = 12 A V GS = 10 V R G = 4.7 (Resistive Load, see fig. 3) Vclamp = 80 V I D = 15 A V GS = 10 V R G = 4.7 (Induct ive Load, see fig. 5) Min. Typ. 49 17 43 36 39 Max. Unit ns ns ns ns ns
SOURCE DRAIN DIODE
Symbo l ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 15 A V GS = 0 100 375 7.5 I SD = 15 A di/dt = 100 A/s T j = 150 o C V DD = 50 V (see test circuit, fig. 5) Test Con ditions Min. Typ. Max. 15 60 1.5 Unit A A V ns nC A
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operatingarea
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STD15NF10
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STD15NF10
TO-252 (DPAK) MECHANICAL DATA
mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397
DIM.
H
A
C2
C
DETAIL "A"
A1
L2
D DETAIL "A" B
=
=
3
B2
=
=
G
E
2
L4
1
=
=
A2
0068772-B
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STD15NF10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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